Lateral PNP bipolar transistors (LPNPs) are desired for many mixed signal integrated circuit (IC) designs. Mixed signal ICs combine both digital and analog circuitry and thus typically comprise CMOS transistors as well as NPN bipolar transistors, high performance capacitors, LPNPs and sometimes resistors. LPNPs may be used in applications such as current mirrors, active loads, and complementary bipolar logic. An example of a critical circuit application for a LPNP is the filter null circuit where the LPNP current mirror has been shown to out-perform the best design using a PMOS based current mirror. The LPNP has higher dynamic range, higher transconductance, lower parasitic capacitance, low operating voltage, higher bandwidth (3X PMOS), less gain variation due to output voltage, and lower DC offset voltage. As a result, LPNPs are very desirable for hard disk drive (HDD) applications.
A typical LPNP design for a mixed signal IC is shown in FIG. 1. Because the LPNP is formed using a BiCMOS process, the formation of the LPNP is designed to use as many of the steps for forming the CMOS transistors as possible. A N+ buried layer 14 is formed in a substrate 12 and functions as the low resistance base of the LPNP 10. N-well 16 is the base of the LPNP 10. The emitter 18 and collector 20 are formed in N-well 16 using a standard p+ source/drain (S/D) implant. The polysilicon (poly) gate electrode 22 is tied to the emitter region 18. LPNP 10 is essentially an inherent PNP of a PMOS transistor optimized for PNP performance. Isolation regions 24 isolate LPNP 10 from other devices (not shown) and from the base contact 26.
There are two dominant currents in LPNP 10. The first is the base or parasitic current. The base current is the electrons and holes injected vertically between the n-well 16 and emitter 18 junction area. The second dominant current is the collector or active current. The collector current is the holes diffused laterally through the "channel" region 28 of the base n-well 16 between the emitter 18 and collector 20.
LPNPs achieve gain from the active current. However, the gain is reduced by the parasitic current. The gain (beta) of the LPNP is proportional to the ratio of the periphery to the area of the emitter S/D diffusion or the ratio of the active to parasitic base-emitter junction. As a result, Beta is proportional to 1/(length of the polysilicon gate):1/(base width). Accordingly, the gain (beta) can be increased by decreasing the poly gate length. However, since the collector and emitter profiles are constant (i.e., fixed by the CMOS design parameters), the early voltage is proportional to the length of the polysilicon gate 22. (The early voltage is proportional to the sum of the active base doping.) Thus, increasing the gate length improves the early voltage. As a result, the beta*early voltage product, a measure of the performance of the LPNP, is relatively constant for a given CMOS technology regardless of base width.
The LPNP typically uses a layout having a circular collector to improve the periphery to area ratio of the emitter. FIG. 2 shows a cross-section of a circular collector LPNP 10 and FIG. 3 is a top view of the same device. A gate length of 0.6 microns results in a beta (gain) of 16 and an early voltage of 12, for a total product of 192. If the gate length is increased to 0.8 microns, the beta is 9 and the early voltage is 20 for a product of 180. The different is relatively insubstantial. For HDD applications, both a beta and early voltage of 20 is desired. Accordingly, improvements in the gain and/or early voltage are needed without substantial increases in process cost.